1. Field of the Invention
The present invention relates to a semiconductor memory, and more particularly to a semiconductor memory, in which electrons are injected into floating gates and are discharged by electrical action or by irradiation of ultraviolet rays. The gates of a plurality of such variable-threshold nonvolatile semiconductor memory transistors are connected to each other in the rows of a matrix and the drains of the transistors are connected to each other in the columns of the matrix.
2. Background Art
FIG. 1 shows an electric circuit diagram of a conventional semiconductor memory. FIG. 2 shows the characteristic relations of a normal memory cell. FIG. 3 shows the characteristic relations of a normal memory cell and a low-threshold memory cell.
The semiconductor memory shown in FIG. 1 is an erasable and electrically-programmable read-only memory (which is hereinafter often referred to as an EPROM) composed of memory cells Q.sub.11 -Q.sub.nm of the FAMOS-type. The gates of the memory cells Q.sub.11 -Q.sub.nm are connected to each other along the rows of a matrix. Word line signals WL.sub.1 -WL.sub.n for selecting the rows are applied to the gates of all the cells on that row. The drains of the memory cells Q.sub.11 -Q.sub.nm are connected to each other along the columns of the matrix so that the columns are used as bit lines BL.sub.1 -BL.sub.m. Column selection signals CS.sub.1 -CS.sub.m for selecting the bit lines BL.sub.1 -BL.sub.m are applied to the bit lines through column selection gates 1-m. The drains of all the column selection gates 1-m are jointly connected to a sense amplifier 20.
The column selection signals CS.sub.1 -CS.sub.m and the word line signals WL.sub.1 -WL.sub.n are generated, as shown in FIG. 2, by a column decoder 10 and a row decoder 12 receiving address signals A.sub.o -A.sub.q. The column decoder 10 selects one of the m column selection signals CS.sub.1 -CS.sub.m for each unique combination of the p address signals A.sub.o -A.sub.p-1. Similarly, the row decoder 12 selects one of the n word line signals WL.sub.1 -WL.sub.n for each unique combination of the (q-p+1) address signals A.sub.p -A.sub.q. Thus, one column and one row is selected for each address signal.
To read information programmed in the EPROM, the word line for the memory cell at a desired address is selected and supplied with an ordinary power voltage of 5 V while all the other word lines are not selected and are supplied with ordinary ground potential of (0 V). Also, only the bit line for the memory cell at the desired address is selected by the column selection signal and is connected to the sense amplifier 20.
FIG. 3 shows the characteristic relations A and B between the gate voltage of the memory cell (the voltage of the word line) and the drain current of the memory cell. When the threshold level of the memory cell in the erased state of "1" is about 1.5 V, the characteristic relation A is obtained. When the threshold level of the memory cell in the programmed state of "0" is about 6 to 10 V, the other characteristic relation B is obtained. A sense current I.sub.sense has such a level for the sense amplifier 20 as to detect the drain current of the memory cell Q.sub.11 -Q.sub.nm to find out whether the information in the memory cell is "1" or "0". When the word line voltage, which is ordinarily 5 V, is applied to the gate of the memory cell Q.sub.11 -Q.sub.nm, the memory cell in the erased state shown by the characteristic relation A in FIG. 3 has a drain current I.sub.M larger than a sense current I.sub.sense, so that the information on the memory cell is judged to be "1". Similarly, the memory cell in the programmed state shown by the characteristic relation B in FIG. 3 has a negligible drain current I.sub.M, so that the information on the memory cell is judged to be "0".
Detailed operation of the EPROM is hereafter described with reference to FIG. 1. When the address of the memory cell Q.sub.11 is selected, the word line signal WL.sub.1 is selected, the other word line signals WL.sub.2 -WL.sub.n are not selected, the column selection signal CS.sub.1 is selected and the other column selection signals CS.sub.2 -CS.sub.m are not selected. As a result, the bit line BL.sub.1 is selected and connected to the sense amplifier 20. If the memory cell Q.sub.11 is the erased state of "1", the memory cell has the characteristic relation A shown in FIG. 3, and since the gate voltage is 5 V, the drain current I.sub.M exceeds the sense current I.sub.sense. For that reason, the sense amplifier 20 judges the information in the memory cell Q.sub.11 to be a "1". At that time, whether the other memory cells Q.sub.21 -Q.sub.n1 on the same bit line BL.sub.1 are in the erased state of "1" or in the programmed state "0", their gate voltages are 0 V so that the drain current I.sub.M does not flow through them. For that reason, reading the information on the memory cell Q.sub.11 is not affected by the other memory cells. If the memory cell Q.sub.11 is in the programmed state of "0", the memory cell has the characteristic relation B shown in FIG. 3, and its gate voltage is 5 V so that the drain current I.sub.M does not flow, namely, the drain current is smaller than the sense current I.sub.sense. For that reason, the sense amplifier 20 judges the information on the memory cell Q.sub.11 to be a "0". At that time, the other memory cells on the same bit line have a negligible drain current I.sub.M for the saem reasons as described above, so that the other memory cells do not affect reading the information on the memory cell Q.sub.11.
However, in practice the memory cells Q.sub.11 -Q.sub.nm actually have irregularities. Although the ordinary threshold voltage of the memory cell in the erased state is about 1.5 V, the threshold voltages of some memory cells are 1 to 2 V higher or lower than the ordinary threshold voltage. Since the erased state of the memory cell with a higher threshold voltage is equivalent to its incompletely programmed state, the memory cell can be easily eliminated as a defective memory by "Erase Check". "Erase Check" means reading the memory cell in the erased state below the power supply voltage of 5 V. In contrast, it is difficult to eliminate a defective memory by erasure if the memory cell has a lower threshold voltage.
Reading the information on the memory cell Q.sub.11 is hereafter described. Suppose that the memory cell Q.sub.11 is normal and in the erased state of "1" but that the memory cell Q.sub.21 is abnormal with the threshold voltage of the memory cell Q.sub.21 being about -1.5 V. Assume that the other memory cells Q.sub.31 -Q.sub.n1 on the same bit line are normal and either in the erased state of "1" or in the programmed state of "0". Since the erased memory cell Q.sub.11 is selected, it has a characteristic relation A shown in FIG. 3 so that when its gate voltage becomes 5 V, its drain current I.sub.M exceeds the sense current I.sub.sense, and the sense amplifier 20 judges the information in the memory cell Q.sub.11 to be a "1". At that time, if the unselected memory cell Q.sub.21 has a characteristic relation C shown in FIG. 4, an electrical current larger than the sense current I.sub.sense flows in the memory cell Q.sub.21 even though an unselected word line voltage of 0 V is applied to it. Although the electrical current is added to the drain current I.sub.M from reading the information on the memory cell Q.sub.11, it does not affect reading the information of "1" on the memory cell Q.sub.11, because the sense amplifier 20 judges the information on the memory cell Q.sub.11 to be "1" if an electrical current equal to or larger than the sense current I.sub.sense flows. For the same reason, reading the stored information of "1" from the memory cell Q.sub.11 is not affected even if the drain current I.sub.M larger than the sensor current I.sub.sense flows in each of the other memory cells Q.sub.31 -Q.sub.n1.
However, suppose that the memory cell Q.sub.11 is normal and in the programmed state of "0", and the threshold voltage of the other memory cell Q.sub.21 is about -1.5 V. Since the memory cell Q.sub.11 is selected, it has a characteristic relation B shown in FIG. 4, so that when its gate voltage becomes 5 V, its drain current I.sub.M does not flow. However, the memory cell Q.sub.21 has the characteristic relation C so that an electrical current larger than the sense current I.sub.sense flows even if the gate voltage is 0 V. As a result, the sense amplifier 20 regards the drain current of the memory cell Q.sub.21 so that of the memory cell Q.sub.11 so that the same amplifier misjudges the information on the memory cell Q.sub.11 to be a "1". For that reason, correct reading cannot be performed.
However, programming can be performed into even such depletion-type memory cell. For that reason, when the memory cell Q.sub.21 is in the programmed state, its threshold voltage is 6 V or more so that the information on the memory cell Q.sub.21 can be also correctly read without affecting the other memory cells on the same bit line. Even when the memory cell Q.sub.21 is in the erased state, reading the information on the memory cell Q.sub.21 is not itself a problem because the drain current of the memory cell Q.sub.21 is only larger than that of a memory cell in the normal erased state.
When an abnormal memory cell of such kind is to be eliminated in an inspection test, a method described below has been conventionally adopted. In the method, all the memory cells Q.sub.11 -Q.sub.nm are first put in the erased state, programming is performed into only one of the memory cells on the bit lines BL.sub.1 -BL.sub.m, and the information on the memory cell in the programmed state is read, so that the other memory cells can be checked. After that, programming is performed into one of the other memory cells on the bit lines, and the information on the memory cell in the programmed state is read, so that the memory cells subjected to the programming and the erasure can be checked. All the memory cells can thus be checked. Although the memory cells can be tested by repeating the programming and the erasure twice, the efficiency of the test is not high, because it is time-consuming to repeat the programming and the erasure.